Low-voltage switched-capacitor circuits

One of the key limitations of state-of-the-art fine linewidth CMOS technologies is the restricted power-supply voltage, limited by the low junction-breakdown voltage of the process and by the thin gate oxide, prone to voltage stress and breakdown. Also, in some applications, the available external power source may limit the supply voltage; for example, this source may be a 1.2 V battery, with an end-of-life voltage of only 0.9 V. In analog and mixed analog-digital circuits, the circuit technique most often used for analog signal processing is based on switched-capacitor (SC) stages. They can be utilized in many applications, such as data conversion (both in Nyquist-rate and oversampled AX ADCs), analog filters, sensor interfaces, etc. However, there are fundamental limitations on the operation of switches when the supply voltage becomes less than the sum of the absolute values of the PMOS and NMOS threshold voltages [ 11. Specifically, if a switch is connected to a signal voltage, which is about half-way between the rail voltages, and V/T,,+/ V T ~ ~ > V d d , i t may not be possible to turn the switch on, even if a CMOS transmission gate is used to realize it. In the past, two approaches have been commonly used to bypass this problem. One used internal voltage boosting (typically, doubling) to obtain high-swing clock signals [2]. This approach is useful if the supply voltage is restricted by the source, as in the case of battery-operated devices, or by the junction breakdown only. However, it cannot be used if the gate oxide deterioration limits the permissible supply voltage. The other alternative was the use of switched op-amps [3]. This approach also suffers from some shortcomings. Specifically, the transients introduced by the required power-up/power-down of the op-amp slow down the operation, increase the required settling time, and thus reduce the speed of the circuit.